EDN

Synopsys ‘pioneers’ SystemVerilog testbench tool

SANTA CRUZ, Calif. — Synopsys Inc. is bringing the “ecosystem” built around its VCS Verilog simulator to users of third-party simulators with Pioneer-NTB, a SystemVerilog testbench automation tool ...
Design-Reuse

Synopsys Advances VCS Solution by Adding Assertion IP Library and Native Testbench Support for SystemVerilog

Latest version of the VCS® solution speeds standards-based verification by unifying SystemVerilog and SystemCâ„¢ languages in a single tool MOUNTAIN VIEW, Calif., May 31, 2005-- Synopsys, Inc. (Nasdaq ...
EDN

Synopsys announces SystemVerilog testbench

At the SNUG (Synopsys Users Group) East meeting this week in Boston, Synopsys will release Pioneer-NTB, its new automatic testbench-verification system supporting the SystemVerilog design and ...
Design-Reuse

SystemVerilog 3.1 adds assertions and testbench automation

The June 2003 release of SystemVerilog 3.1 integrates testbench automation capabilities and temporal assertions into an enhanced version of Verilog. It eliminates many of Verilog's past limitations, ...
Electronic Design

Tool Automates Generation Of SystemVerilog Testbenches

THE SYSTEMVERILOG INFRASTRUCTURE is built out further with Synopsys' introduction of Pioneer-NTB. This testbenchautomation tool delivers native SystemVerilog testbench generation to users of ...
New Electronics

Structured messages ease SystemVerilog testbench debug

In the latest release of its Verdi automated debug system, eda specialist SpringSoft has it is providing 'comprehensive SystemVerilog Testbench (SVTB) debug support'. Fully integrated with the company ...
Finanznachrichten

ADVISORY/Synopsys to Deliver Keynote, Lead SystemVerilog Tutorials at DVCon 2006

The conference's general chair is Karen Bartleson, director of interoperability, also of Synopsys. In addition, the company will deliver SystemVerilog tutorials and functional verification papers that ...